In present semiconductor technology, CMOS devices, such as n-channel FETs (n-FETs) and p-channel FETs (p-FETs), are typically fabricated upon semiconductor wafers comprised of single crystal semiconductor materials.
In single crystal semiconductor materials, all lattice directions and lattice planes in a unit cell of a single crystal material can be described by a mathematical description known as a Miller Index. Specifically, the notation [hkl] in the Miller Index defines a crystal direction or orientation. FIG. 1 shows a single crystal silicon unit cell, which is a cubic cell. Certain crystal directions, such as [001], [100], [010], [110], and [111], are specifically indicated by arrowheads in the cubic unit cell. Moreover, the crystal planes or facets of a single crystal silicon unit cell are defined by the notation (hkl) in Miller Index, which refers to a particular crystal plane or facet that is perpendicular to the [hkl] direction. FIG. 2 illustratively shows the crystal planes (100), (110), and (111) of the single crystal silicon unit cells, which are respectively perpendicular to the [100], [110], and [111] directions. Further, because the unit cells are periodic in a semiconductor crystal, there exist families or sets of equivalent crystal directions and planes. The notation <hkl> in the Miller Index therefore defines a family or set of equivalent crystal directions or orientations. For example, the <100> directions include the equivalent crystal directions of [100], [010], and [001]; the <110> directions include the equivalent crystal directions of [110], [011], [101], [−1−10], [0−1−1], [−10−1], [−110], [0−11], [−101], [1−10], [01−1], and [10−1]; and the <111> directions include the equivalent crystal directions of [111], [−111], [1−11], and [11−1]. Similarly, the notation {hkl} defines a family or set of equivalent crystal planes or facets that are respectively perpendicular to the <hkl> directions. For example, the {100} planes include the set of equivalent crystal planes that are respectively perpendicular to the <100> directions.
Semiconductor wafers typically each has a substrate surface oriented along one of a single set of equivalent crystal planes of the single crystal semiconductor material (e.g., Si) that forms the wafers. In particular, most of today's semiconductor devices are built upon silicon wafers having wafer surfaces oriented along one of the {100} crystal planes of silicon. However, electrons are known to have a high mobility along the {100} crystal planes of silicon, but holes are known to have high mobility along the {110} crystal planes of silicon. Specifically, hole mobility values along the {100} planes are roughly about 2 to 4 times lower than the corresponding electron hole mobility values along such planes. Furthermore, hole mobility values along the {110} silicon surfaces are about 2 times higher than those along the {100} silicon surfaces, but electron mobility along the {110} surfaces are significantly degraded compared to those along the {100} surfaces.
Therefore, there is a need for providing a semiconductor substrate having different surface orientations (i.e., hybrid surface orientations) that provide optimal performance for different devices.
Further, mechanical stresses within a semiconductor device substrate can also be used to modulate device performance. For example, in silicon, hole mobility is enhanced when the silicon film is under compressive stress in the film direction and/or under tensile stress in a direction normal of the silicon film, while the electron mobility is enhanced when the silicon film is under tensile stress in the film direction and/or under compressive stress in the direction normal of the silicon film. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-FET and/or an n-FET in order to enhance the performance of such devices.
However, the same stress component, either compressive or tensile stress, discriminatively affects the performance of a p-FET and an n-FET. In other words, compressive stress in the source-drain direction and/or tensile stress in the direction normal of the gate dielectric layer enhances the performance of the p-FET, but adversely impacts the performance of the n-FET, while tensile stress in the source-drain direction and/or compressive stress in the direction normal of the gate dielectric layer enhances the performance of the n-FET, but adversely impacts the performance of the p-FET. Therefore, p-FET and n-FET require different types of stresses for performance enhancement, which imposes a challenge for concurrent fabrication of high performance p-FET and n-FET, due to the difficulty in concurrently applying compressive stress in the source-drain direction to the p-FET and tensile stress to the n-FET, or concurrently applying tensile stress in the direction normal of the gate dielectric surface to the p-FET and compressive stress to the n-FET.
Embedded SiGe stressors have been used in the past to induce compressive strain in a p-FET channel region, consistent with the above-described approach. For example, a compressively stressed silicon channel layer can be formed between embedded SiGe stressors that are epitaxially grown over a silicon substrate. The lattice constant of germanium is greater than that of silicon, as shown in FIG. 3. As a result, epitaxial growth of SiGe on a silicon substrate will yield SiGe stressor layers with compressive stress, and the compressively stressed SiGe stressors will in turn apply compressive stress to the channel region located therebetween. For another example, a tensilely stressed silicon channel layer can be formed between embedded Si:C stressors that are epitaxially grown over a silicon substrate. Because the lattice constant of carbon is smaller than that of silicon, as shown in FIG. 3, epitaxial growth of Si:C over a silicon substrate will yield Si:C stressor layers with tensile stress, and the tensilely stressed Si:C stressors will in turn apply tensile stress to the channel region located therebetween.
However, the embedded SiGe or Si:C stressors can only be used to enhance the electron or hole mobility of one type of FETs (either n-type or p-type), but they will deleteriously reduce the carrier mobility in the complementary FETs. Although complementary Si:C or SiGe stressors can be independently formed in the complementary FETs, the use of different stress-inducing materials for the p-FETs and the n-FETs requires additional processing steps, which will significantly increase the processing complexity as well as the manufacturing costs.
There is therefore also a need for using the same stress-inducing materials to generate different stresses (i.e., compressive and tensile) in the n-FETs and the p-FETs for respectively enhancing electron mobility and hole mobility therein.